1. Field of the Invention
The present invention relates to the field of integrated microdevices, such as, but not exclusively, Micro-Electro-Mechanical-Systems (MEMS), and in particular to a novel method of fabricating such devices at the wafer level. The invention is also applicable to the fabrication of biochips and like microdevices.
2. Description of Related Art
The manufacture of MEMS devices, such as micro-gyroscopes, micro-accelerometers, resonant accelerometers, micro-mirrors, micro-motors, micro-actuators and other such micro-devices integrating at least one moving part presents a very serious challenge in terms of packaging. A batch of such devices is fabricated on a wafer using semiconductor technology. The wafer is then diced to form the individual devices. Some MEMS-based devices require the encapsulation (known as wafer level packaging) to be done prior to dicing so that they are protected against contamination from particles and dicing slurry while during subsequent processing without the need for dedicated equipment or processes for dicing, mounting and molding procedures inside clean rooms. In addition, changes in atmospheric conditions can change the capacitance readout of micro-gyroscopes and micro-accelerometers without any corresponding change in acceleration, and because an increased relative humidity can increase stiction (that is the tendency of the moving parts to stick) of their moving parts, it is necessary to encapsulate the moving parts in a vacuum or in a controlled atmosphere.
In order to ensure the above functions, the moving parts are typically enclosed in a sealed micro-cavity under vacuum or under a specific pressure of dry nitrogen, dry forming gas or dry sulfur hexafluoride ambient. This is achieved by bonding two substrates together.
Since many MEMS devices must be operated under a high vacuum for ten years or more at a temperature of up to 150° C., the wafer-level packaging should allow the internal materials of the two substrates to be vacuum treated at a temperature much higher than the maximum operation temperature of 150° C. prior to sealing the wafer-level package under a vacuum in order to reduce the release of water vapor, hydrogen or other gases from these internal materials through this ten years period. In order to maintain the throughput of such vacuum wafer-level packaging process, this vacuum treatment at a temperature of about 400° C. should be followed by the wafer-level packaging bonding at a bonding temperature not too low compared to the 400° C. vacuum treatment so as to minimize the delays due to the cooling of the two substrates to the bonding temperature. A vacuum wafer-level packaging bonding temperature of 300–400° C. would be ideal for these applications.
However, many MEMS devices do not require to be operated under vacuum, and since many of these are very sensitive to the various coefficients of thermal expansion, it would also be desirable to develop an optional lower temperature wafer-level packaging process, which also guarantees reliable service for the expected life of the MEMS device in less stringent situations. Since the typical life of most semiconductor applications is about 10 years up to an operation temperature of up to 150° C., the lower temperature limit of the lower temperature wafer-level packaging process (the temperature at which de-bonding may occur) should not be lower then about 200° C. A non-vacuum wafer-level packaging bonding temperature of 175–300° C. would then be ideal for these applications.
The mechanical component or moving part of a MEMS device is mechanically released from surrounding materials so that it becomes relatively free to move and perform its sensing and/or actuation function. Wafer-level packaging involves the bonding of a sealed protective cap over this mechanical component following its mechanical release from its surrounding materials. Since such MEMS devices are typically fabricated from the combination of various materials having different coefficients of thermal expansion, it is important to minimize the exposure of the MEMS devices to high temperatures since this released component may be affected by the mechanical effects resulting from these various coefficients of thermal expansion Such effects can be observed as out-of-specification sensing or actuation, induced flexion and ultimately stiction between the released component and its surrounding materials, induced mechanical stress or mechanical failures in the released component, and unreliable performance in the field. In order to minimize these undesirable effects, it is necessary to minimize the temperature at which the mechanical component is exposed following its mechanical release from its surrounding materials. An upper limit of about 400° C. is desirable. Such an upper limit of 400° C. clearly limits the use of the well known direct wafer bonding (DWB) technique, which requires a temperature of about 1000 to 1200° C. to bond two polished silicon surfaces. Other lower temperature processes have been developed and are discussed herein. Unfortunately, none of these processes satisfy all the requirements for these special situations.
U.S. Pat. No. 6,232,150 titled ‘Process for making microstructures and microstructures made thereby’ (The Regents of the University of Michigan) as shown in FIG. 1, discloses the local bonding of Dow Corning's Pyrex 7740 glass to a phosphosilicate structure layer at a local temperature ranging between 820° C. and 1300° C. using an underlying polysilicon-based resistive micro-heater capable of locally heating the phosphosilicate bonding material to a high enough temperature as to allow bonding to the upper Pyrex 7740 glass. This reference employs a bonding temperature that is way over the desired upper limit of 400° C. It uses a temperature gradient which is necessarily associated with a mechanical stress gradient in the surrounding structures. Pyrex™ 7740 glass contains a lot of sodium in the form of Na2O and is thus absolutely incompatible with a CMOS line of products. This very serious limitation implies that the fabrication MEMS devices using in accordance with this reference must be limited to a dedicated tool set and cannot simply be introduced into a standard CMOS production line. Moreover, it also implies that this cited Pyrex-based wafer-level packaging technique will limit the development of future MEMS devices integrating optional sensing, control or communication devices and optional high-voltage actuation drivers.
While this patent requires the use of undesirable glasses, the process described is carried out at an excessive local temperature ranging between 820° C. and 1300° C., which may cause undesirable mechanical stress gradient in the surrounding structures.
U.S. Pat. No. 5,952,572 titled ‘Angular rate sensor and acceleration sensor’ (Matsushita Electric Industrial Co., Ltd.) is shown in FIG. 2. Three substrates composing the angular rate sensor described in U.S. Pat. No. 5,952,572 are bonded together as a sandwich structure using anodic bonding, as mentioned in column 7, lines 36–41 of the patent. This anodic bonding requires a Pyrex glass and the silicon and glass substrates to be heated to about 360° C. in a vacuum while a negative voltage of about 1000V is applied to the glass substrate with respect to the silicon substrate to be bonded with it.
This reference also uses Na2O-containing Pyrex glass and is thus also incompatible with CMOS technology. It also limits the development of future MEMS devices integrating optional sensing, control or communication devices and optional high-voltage actuation drivers. Since it requires the use of anodic bonding, it is also undesirable in most situations because substrates have to avoid contaminating the fabrication toolset with undesirable elements in the bonded glass.
FIG. 3 illustrates a Samsung process described in B. Lee, S. Seok, J. Kim, and K. Chun, ‘A mixed micromachined differential resonant accelerometer’, Work supported by ADD (Agency for Defense Development) through ACRC (Automatic Control Research Center) under Grant AC-041 and by the Brain Korea21 Project. Samsung employs a vacuum packaging technique again using the anodic bonding of a handle glass wafer to a Chemical-Mechanical Polished (CMP) 6 μm thick polysilicon layer deposited on a previously deposited and patterned TEOS (tetraethylorthosilicate) sacrificial layer.
FIG. 4 illustrates another Samsung process described in B. Lee, C. Oh, S. Lee, Y. Oh and K. Chun, ‘A vacuum packaged differential resonant accelerometer using gap sensitive electrostatic stiffness change effect’, Work supported by ADD (Agency for Defense Development) through ACRC (Automatic Control Research Center) under Grant AC-041. FIG. 4 shows that Samsung discloses another approach again using the anodic bonding of two substrates to produce accelerometers affected by the presence of residual gas (air) causing an observed damping effect. This paper clearly explains the effect or residual gases on the performance of MEMS devices and clearly explains the need for a vacuum sealed wafer-level package for such applications. Again, the use of this anodic bonding approach using sodium-based Pyrex glass is incompatible with CMOS technology and limits the development of future MEMS devices integrating optional sensing, control or communication devices and optional high-voltage actuation drivers.
The low-temperature bonding technology of Samsung Corporation also requires the use of anodic bonding.
FIGS. 5 and 6 show the surface micromachining performed at Robert Bosch GmbH. FIG. 5 shows that a glass frit technique is used to bond a 380 μm thick Cap wafer forming a 75 μm high protective cavity to ann-released section of a 10.3 μm thick polysilicon as to provide an hermetic seal. FIG. 6 shows the glass frit region between the protective Cap wafer and the substrate.
The glass frit technique typically requires a bonding temperature ranging between 350° C. and 475° C., and is slightly higher than the vacuum wafer-level packaging bonding temperature of 300–375° C. and certainly much higher than the non-vacuum wafer-level packaging bonding temperature of 175–300° C. Moreover, the vacuum performance of the dielectrics used in this glass frit bonding technique is questionable for vacuum wafer-level packaging bonding because low-temperature glasses are well known to be porous and thus not really suitable for use as vacuum-tight materials. A metal-based bonding technique compatible with vacuum applications would be preferred.
FIG. 7 is taken from U.S. Pat. No. 5,668,033 titled ‘Method for manufacturing a semiconductor acceleration sensor device’. FIG. 7 shows that a machined cap silicon wafer covered with gold can be bonded to the silicon layer of a silicon-on-insulator (SOI) substrate in order to protect the underlying released MEMS structure.
FIG. 8 shows a gold-silicon phase diagram taken from the http://metal.or.kr/college/m etc/ele-index.html. This gold-silicon phase diagram indicates that when a clean oxide-free silicon surface is brought into intimate contact with a gold surface at a temperature of more than 360° C., a liquid silicon-gold eutectic phase will appear at the interface. Cooling the interface to a temperature lower than 360° C. will result in bonding.
This process described in this document indicates that an underlying silicon oxide diffusion barrier layer is formed on the bottom surface of the machined cap silicon wafer to prevent the diffusion of gold into the silicon of this machined cap silicon wafer and the associated voids thus created during the bonding process (column 7, lines 18–30). In order to enhance the adhesion of gold on this underlying oxide layer, a 0.1 μm thick titanium, nickel or chromium adhesion layer is deposited between the oxide diffusion barrier layer and the 2 to 5 μm thick gold layer deposited by a plating technique. The patterning of 100 to 300 μm wide gold bonding patterns is then performed using standard photolithography (column 6, lines 28–43).
This reference also indicates that these 100 to 300 μm wide gold bonding patterns are faced and aligned to corresponding silicon patterns of slightly larger width under vacuum or inert-gas atmosphere at a prescribed pressure and then pressed at a temperature of about 400° C. using a force of about 0.2 to 1.0 kg/mm2 for a period of tens of minutes before cooling below the eutectic temperature of 363° C.
The underlying silicon oxide diffusion barrier layer formed on the bottom surface of the machined cap wafer to prevent the diffusion of gold during the bonding process in undesirable for several reasons. Firstly, it constitutes another potential source of hydrogen or water vapor which limits the life of the sealed device. It decreases the infrared transparency of the overlying silicon substrate and then prevents the use of this wafer-level packaging technique for MEMS-based optical telecommunication switches operating in the C-Band (1300 nm), L-Band (1550 nm) and L-Band (1625 nm). It implies the contamination of a wet etch tool with gold if the underlying silicon oxide layers needs to be removed (i.e. as, for example, to allow the wafer-level packaging to be used for telecommunication infrared switches). In fact, this barrier layer is not really necessary because there are metal-based barrier metals which can be used under the gold layer and over the silicon layer to eliminate the interaction between gold and the silicon of the machined cap silicon wafer during the bonding process.
The photolithography of the gold layer, of the underlying 0.1 μm thick titanium, nickel or chromium adhesion layer and of the underlying silicon oxide diffusion barrier layer is undesirable because it implies gold contamination of the following of the equipment typically located in the CMOS fabrication area, namely the photoresist coater, scanner or stepper exposure equipment, develop equipment, etcher, photoresist stripper and surface cleaner.
FIG. 9 is taken from U.S. Pat. No. 6,265,246 titled ‘Microcap wafer-level package’ (Agilent Technologies, Inc.). The base wafer integrating a micro-device described in this patent is bonded to a matching cap wafer using cold welding of the bonding pad gaskets of the cap wafer to the periphery of the bonding pads of the base wafer integrating the micro-device. The arrangement assures an hermetic seal of the wafer-level package and electrical connections to the micro-device without passing through a seal. The bonding pads and bonding gaskets are selected from the following list of materials: silicon, aluminum, copper, gold, silver, alloys of these or compounds of these.
The following is the list of the possible binary combinations of bonding pairs of elements disclosed by Agilent's U.S. Pat. No. 6,265,246: silicon-aluminum; silicon-copper; silicon-gold; silicon-silver; aluminum-copper; aluminum-gold; aluminum-silver; copper-gold; copper-silver; gold-silver;
FIG. 10 shows the phase diagrams of the upper four pairs of elements involving silicon (silicon-aluminum; silicon-copper; silicon-gold; silicon-silver), as found at http://metal.or.kr/college/m etc/ele-index.html.
The silicon-aluminum pair has an eutectic temperature of about 580° C. The silicon-copper pair has an eutectic temperature of about 802° C. The silicon-gold pair has an eutectic temperature of about 360° C. and the silicon-silver pair has an eutectic temperature of about 835° C. It is clear that, out of these four pairs, the most interesting is still the silicon-gold pair, already disclosed by Nippon Denso's U.S. Pat. No. 5,668,033.
FIG. 11 shows the phase diagrams of two out of the three other pairs of elements involving aluminum (aluminum-copper; aluminum-gold; aluminum-silver), that can be found at http://metal.or.kr/college/m etc/ele-index.html.
The aluminum-copper pair has an eutectic temperature of about 548° C. The aluminum-gold pair is unstable and results in the so called purple plague. The aluminum-silver pair has an eutectic temperature of about 567° C. It is clear that none of these pairs is more interesting than the silicon-gold pair already disclosed by Nippon Denso's U.S. Pat. No. 5,668,033.
FIG. 12 shows the phase diagrams of the two other pairs of elements involving copper (copper-gold; copper-silver). The copper-gold pair has an eutectic temperature of about 910° C. The copper-silver pair has a eutectic temperature of about 780° C. It is clear that none of these pairs is more interesting then the silicon-gold pair already disclosed by Nippon Denso's U.S. Pat. No. 5,668,033.
FIG. 13 shows the phase diagrams of the remaining pair of elements involving gold (gold-silver. It is clear that the gold-silver pair is not more interesting then the silicon-gold pair already disclosed by Nippon Denso's U.S. Pat. No. 5,668,033.
None of the metal combinations disclosed in the U.S. Pat. No. 6,265,246 has a eutectic temperature lower than the silicon-gold pair already disclosed by Nippon Denso's U.S. Pat. No. 5,668,033.
Contrary to previously discussed Nippon Denso's U.S. Pat. No. 5,668,033, U.S. Pat. No. 6,265,246 does not describe the use of an underlying silicon oxide diffusion barrier layer formed on the bottom surface of the 200 μm thick matching cap wafer to prevent the diffusion of gold during the bonding process. The elimination of the silicon oxide diffusion barrier layer eliminates the potential source of hydrogen or water vapor which limits the life of the sealed device. It also prevents the decrease of the infrared transparency of the overlying silicon substrate and allows the use of this wafer-level packaging technique for MEMS-based optical telecommunication switches operating in the C-Band (1300 nm), L-Band (1550 nm) and L-Band (1625 nm). Finally, the elimination of the silicon oxide diffusion barrier layer prevents the contamination of a wet etch tool with gold if the underlying silicon oxide layers needs to be removed (for example, to allow the wafer-level packaging to be used for telecommunication infrared switches).
FIG. 14 shows the process sequence described by Agilent Technologies for the fabrication of a matching cap wafer. A first coat of photoresist is coated onto the silicon wafer, exposed and developed. A deep silicon etch is performed so as to penetrate about 100 μm into the 200 μm thick silicon wafer and produce a series of deep trench patterns. Following photoresist stripping, a very thin diffusion barrier layer of chromium, nickel or titanium is deposited by sputtering just before the in-situ deposition, in the same sputtering equipment, of a 0.2 to 0.3 μm of gold seed layer (column 4, lines 1 to 9). A second pattern of thick high-viscosity photoresist is then coated, exposed and developed onto this gold seed layer to allow the electroplating of a thick pattern of gold into the developed pattern of photoresist, using the seed gold layer as electrode. Following plating, the photoresist is removed using conventional photoresist stripping, thus leaving a gold pattern whose thickness is only limited by the thickness of the high-viscosity photoresist. The remaining gold seed layer and metal-based diffusion barrier layer are etched away using a conventional etching process. The passages at column 4, lines 60 to 67, and column 5, lines 1 to 11 teach that, an adhesion layer (not shown) can be deposited on the base wafer and that an unspecified material be deposited by sputtering or evaporation. Patterning is done by photolithography, the unwanted unspecified conductive material is etched away, and the photoresist is removed. Alternately, the photolithography is performed, followed by the deposition of the adhesion layer and the unspecified conductive material, followed by the removal of the photoresist material and of the unwanted unspecified conductive material to form the bonding pads.
As described in column 5, lines 12 to 18, and as shown in FIG. 15 the matching cap wafer is turned-over and aligned to the base wafer and compressed together at temperatures up to 350° C. until “cold weld” bonding occurs for the gold plated pattern of the matching cap wafer to bond to the unspecified material of the bonding pad of the base wafer and create a completely hermetically sealed volume for the protected microdevice. The matching cap wafer is then thinned using conventional wafer grinding or lapping and polishing so that the previously deep etched trench patterns extend all the way through the matching cap wafer.
The above description of the bonding technique does not allow a person skilled in the art of bonding to reproduce the results stated without knowing the nature of the material deposited on the base wafer the technique used to “remove” this unwanted material following photoresist removal.
FIG. 16 is taken from U.S. Pat. No. 6,297,072. FIG. 16 shows that the so called “Indent-Reflow-Sealing” (IRS) technique described in this patent uses a first chip located on a first substrate fabricated by depositing and patterning a metallization seed layer; preparing a polyimide mold to define the solder ring; and electroplating the solder ring in the mold using an optional nickel spacer whose thickness is only limited by the thickness of the polyimide mold. Preferably the eutectic 63% tin-37% lead solder, but alternately one of the following solders: 5% tin-95% lead, tin-lead-2% Silver, indium, 80% gold-20% tin, tin-silver, tin-silver-copper or tin-bismuth can be used. After removal of the polyimide mold, a shearing tool or an indenter is used to create an indent region in the electroplated solder ring, as shown in FIG. 17. This indent later disappears during the later reflow of this solder ring.
A second chip located on second substrate is then fabricated. As shown in FIG. 18, first there is carried out the deposition and patterning of a suitable metal ring adequately wettable and capable of forming a stable intermetallic compound with the electroplated (electrodeposited) solder ring of the first chip of the first substrate. Examples of a suitable metal ring are most stable tin-copper or alternately, tin-nickel covered with a thin layer of 0.1–0.3 μm of gold to prevent nickel oxidation. A tin-nickel/gold metal ring with a gold layer thicker than 0.3 μm will result in an unreliable solder connection.
A pre-treatment “flip-chip” alignment is carried out after suitable plasma treatment of both substrates to enhance adhesion following reflow of the solder ring. As shown in FIG. 19, a flip-chip aligner and bonding system is used to make the solder ring of the first chip of the first substrate face and be aligned with the metal ring of the second chip of the second substrate.
As a pre-bonding step, both chips are heated to a temperature well below the melting point of the solder ring (a softening temperature well below the reflow temperature), such as 120–160° C. for a 67% tin-37% lead. Pre-bonding is then carried out by the application of a bonding force (typically 2 kgf or 19.62 N) for the two chips of the two substrates so that they stick as shown in FIG. 20. This allows the pair to be moved to the reflow oven. The temperature and bonding force is optimized for the chosen solder ring, the solder ring history and the type of metal ring used.
In the reflow oven, the cavity formed between the aligned and pre-bonded solder ring and metal ring is evacuated and then filled with the required pressure of desired gas, such as nitrogen, nitrogen-hydrogen mixtures or sulphur hexafluoride. Alternately, the vacuum cavity can be vacuum evacuated. FIG. 21 shows that the evacuation and filling of the cavity is performed through the indent region previously created in the solder ring.
The temperature of the oven is raised to about or above the melting point of the solder ring but below the melting point of all other materials used. As shown in FIG. 22, the solder ring melts to close the indent region resulting in a hermetically sealed cavity with a controlled ambient. The result is the eutectic bonding between the electroplated 67% tin-37% lead solder ring and the 0.1–0.3 μm gold layer of the tin-nickel/gold metal ring.
This patent then describes the bonding of an indented 63% tin-37% lead, 5% tin-95% lead, tin-lead-2% silver, indium, 80% gold-20% tin, tin-silver, tin-silver-copper or tin-bismuth solder ring electroplated over an optional electroplated nickel spacer of a first substrate to a tin-copper or tin-nickel/gold metal ring of a second substrate using two pieces of equipment: a single-wafer pre-bonder and a batch oven to seal the indented solder ring by reflow under a controlled pressure of nitrogen, nitrogen-hydrogen or sulphur hexafluoride or under vacuum.
The use of the solder ring on the first substrate allows the bonding to the tin-copper or tin-nickel/gold metal ring of the second substrate to be performed at temperatures that are much lower then the gold-silicon eutectic temperature of 363° C.
Unfortunately, there are a couple of issues with the above bonding strategy. It is yet not clear which of the two substrates (the substrate with the solder ring or the substrate with the metal ring) would integrate the MEMS structure to be mechanically released using vapor HF. If it is the solder ring, then the electroplated solder material would be exposed to vapor HF. Unfortunately the exposure of a noble metal (such as gold) to vapor HF would be preferred. If it would be the tin-copper or tin-nickel/gold metal ring then either a tin-copper or tin-nickel/gold structure would then be exposed to vapor HF. The first tin-copper situation is undesirable because it does involve the exposure of a noble metal to vapor HF. The second tin-nickel/gold situation is more desirable because it implies that gold would be exposed to vapor HF. Unfortunately, the underlying metal would then be tin-nickel, which is not a desirable choice.
FIG. 23 shows the phase diagram of the tin-nickel system. FIG. 23 shows that the exposure of tin-nickel to temperatures in excess of 231° C. results in the formation of liquid tin under the gold layer, which is absolutely undesirable if the bonding is to be performed to the upper gold layer.
The above described technique requires the precise indentation of the solder ring to allow the two substrates to be aligned. They must then be pressed together, and heated to a softening temperature so as to stick the two substrates together in the alignment and pre-bonding equipment. This step is followed by the formal reflow of the solder ring at the required pressure of nitrogen, nitrogen-hydrogen or sulphur hexafluoride gas or under proper vacuum level in another batch reflow equipment. This complex indentation process, align-press-heating pre-bonding step in one equipment and this release of the applied force and reflow in an independent batch reflow equipment has a number of disadvantages. The process is very complex; of questionable reliability because the applied force is released before the actual reflow of the solder ring, thus allowing the various interfaces to be “de-stick” during manipulation and loading into the batch reflow oven; and unnecessarily costly to manufacture.
The review of the prior art indicates that it is associated with several problems. The well known direct wafer bonding (DWB) technique requiring a bonding temperature of about 1000 to 1200° C. operates at too a high temperature to be used for MEMS involving a mechanically released sensitive structure.
The technique described in U.S. Pat. No. 6,232,150 involving the bonding of Dow Corning's Pyrex 7740 glass using a polysilicon-based resistive micro-heater capable of locally bonding silicon to this Na2O-based phosphosilicate requires an excessively high local temperature ranging between 820° C. and 1300° C. This technique is undesirable for many reasons: It causes undesirable mechanical stress gradients in the region of the mechanically released sensitive structure; its Na2O-based Pyrex 7740 glass is absolutely incompatible with CMOS technology. It also limits the development of future MEMS devices integrating optional sensing, control or communication devices and optional high-voltage actuation drivers because its structural sodium contaminates the manufacturing equipment with sodium and results in devices affected by sodium-induced threshold voltage instabilities and sodium-induced slow trapping reliability problems.
The anodic bonding process described in U.S. Pat. No. 5,952,572 (Matsushita Electric Industrial Co., Ltd.) and in the two Samsung Prior Art publications B. Lee, S. Seok, J. Kim, and K. Chun, ‘A mixed micromachined differential resonant accelerometer’, Work supported by ADD (Agency for Defense Development) through ACRC (Automatic Control Research Center) under Grant AC-041 and by the Brain Korea21 Project; B. Lee, C. Oh, S. Lee, Y. Oh and K. Chun, ‘A vacuum packaged differential resonant accelerometer using gap sensitive electrostatic stiffness change effect’, Work supported by ADD (Agency for Defense Development) through ACRC (Automatic Control Research Center) under Grant AC-041; allows the reduction of the bonding temperature of the Na2O-based Pyrex 7740 glass to about 360° C. using vacuum anodic bonding. This anodic bonding process has the same sodium-related contamination issues and the same limitations concerning the development of future MEMS devices integrating optional sensing, control or communication devices and optional high-voltage actuation drivers. Moreover, this technique requires the application of undesirable high voltage gradients (1000 to 2000 volts). Added to this sodium-based limitation, the anodic bonding process requires a 1000 to 2000 volts voltage drop to be applied between the Pyrex 7740 glass and the fresh silicon surface to be bonded.
A glass frit bonding technique reported by Robert Bosch GmbH in the following two prior art publications reduces the bonding temperature to a range between 350° C. and 475° C. This temperature is still slightly higher than the vacuum wafer-level packaging bonding temperature of 300–375° C. and certainly much higher then the non-vacuum wafer-level packaging bonding temperature of 175–300° C. Moreover, the vacuum performance of the dielectrics used in this glass frit bonding technique is questionable for vacuum wafer-level packaging bonding situations because low-temperature glasses are well known to be porous and not really suitable as vacuum-tight materials.
The silicon-gold eutectic bonding technique reported in U.S. Pat. No. 5,668,033 (Nippon Denso Co., Ltd.) describes a process involving the bonding of a cap silicon wafer to a base wafer. The bottom surface (bonding side) of the cap wafer is covered with a silicon oxide layer preventing the diffusion of gold into silicon and associated voids created during the bonding process. To enhance the adhesion of gold on this underlying oxide layer, a 0.1 μm thick titanium, nickel or chromium layer is deposited between the oxide diffusion barrier layer and the gold layer. Standard photolithography is used to pattern the gold bonding patterns before flipping the cap wafer, aligning the gold bonding patterns to the facing silicon patterns of the base wafer and pressing these gold patterns to these silicon patterns at a temperature of about 400° C. for tens of minutes before cooling below the eutectic temperature of 363° C. This fabrication technique of the cap silicon wafer and of the base silicon wafer (free from native oxide) has serious limitations which cannot provide a stable and repeatable bonding. This limitation is acknowledged by the inventors of this patent who describe the use of an hydrofluoric acid based etching solution to eliminate the natural oxide formed on the surface of these facing silicon patterns (column 5, lines 53 to 56). Since the base wafer typically incorporates hundreds of sensitive and mechanically released MEMS structures, it is generally not possible to use hydrofluoric acid based etching solutions because their surface tension will cause the surface of the released MEMS structure and the surface of surrounding structures to stick together, a well known problem in MEMS fabrication. Since this native oxide naturally re-grows in ambient conditions over a typical time period of a few hours (a time period equivalent to the bonding of a couple of pairs of wafers at a typical throughput of a few tens of minutes per pair of wafers) and since there are typically forty-eight wafers to bond in succession (one set of twenty-four cap wafers to bound to one set of twenty-four base wafers) the native oxide can then re-grow during delays between steps, during manipulations and even while bonding the first pairs of wafers. The eutectic bonding of gold to bare silicon is then a non-repeatable and unstable process requiring a lot of special precautions which, thus not desirable. If this MEMS device is a photonics MEMS device (such as a MEMS-based optical telecommunication switch) requiring the cap wafer to be infrared transparent in the C-Band (1300 nm), L-Band (1550 nm) and L-Band (1625 nm) then the underlying silicon oxide diffusion barrier layer formed on the bottom surface of the cap wafer as to prevent the diffusion of gold during the bonding process in also undesirable because it will increase the absorption loss of the switch. If the MEMS device is a vacuum-based automotive device such as a micro-gyroscope, then the presence of the underlying silicon oxide diffusion barrier layer formed on the bottom surface of the cap wafer will also constitute a potential source of hydrogen or water vapor which and then limit the life of the vacuum-sealed device. Finally, the use of standard photolithography to pattern the gold layer and the underlying 0.1 μm thick titanium, nickel or chromium adhesion layer is undesirable because it implies gold contamination of the following list of equipment typically located in the CMOS fabrication area: photoresist coater, scanner or stepper exposure equipment, develop equipment, etcher, photoresist stripper and surface cleaner.
U.S. Pat. No. 6,265,246 also describes a process involving the bonding of a cap silicon wafer to a base wafer. Unlike Nippon Denso's U.S. Pat. No. 5,668,033, Agilent Technologies' U.S. Pat. No. 6,265,246 describes the use of a very thin diffusion barrier layer of chromium, nickel or titanium as replacement of the silicon oxide diffusion barrier layer, thus eliminating the upper-described issues with this silicon oxide diffusion barrier. The analysis of the various phase diagrams shows that, out of the silicon-aluminum, silicon-copper, silicon-gold, silicon-silver, aluminum-copper, aluminum-gold, aluminum-silver, copper-gold, copper-silver and/or gold-silver possible bonding combinations reported in U.S. Pat. No. 6,265,246, the bonding combination providing the lowest possible bonding temperature is still silicon-gold, with an eutectic temperature of 363° C. Curiously, the passage at column 5, lines 12 to 18 states that the cap wafer is turned-over, aligned to the base wafer and compressed together at temperatures up to 350° C. until “cold weld” bonding occurs for the gold plated pattern of the matching cap wafer to bond to the unspecified material of the bonding pad of the base wafer and create a completely hermetically sealed volume for the protected micro-device. As previously mentioned, the bonding technique does not allow a person skilled in the art of bonding to understand the so-called “cold weld” at temperatures up to 350° C. or to reproduce the results of the patent. Since the “cold weld” temperature is lower than the silicon-gold eutectic temperature of 363° C., the pads cannot be covered by silicon and the wafer-level bonding cannot be performed by silicon-gold eutectic bonding.
The “Indent-Reflow-Sealing” (IRS) technique reported in U.S. Pat. No. 6,297,072 describes a process involving the bonding of an indented 63% tin-37% lead, 5% tin-95% lead, tin-lead-2% silver, indium, 80% gold-20% tin, tin-silver, tin-silver-copper or tin-bismuth solder ring electroplated over an optional electroplated nickel spacer of a cap wafer to a tin-copper or tin-nickel/gold metal ring of a base wafer using two pieces of equipment: a single-wafer pre-bonder and a batch oven to seal the indented solder ring by reflow under a controlled pressure of nitrogen, nitrogen-hydrogen or sulfur hexafluoride or under vacuum. The use of one of the proposed solder rings on the cap wafer allows the bonding to the tin-copper or tin-nickel/gold metal ring of the base wafer at a temperature which is much lower then the gold-silicon eutectic temperature of 363° C. There are a couple of issues with this metallurgical process. In order to release the mechanical structure of the MEMS, the metal ring of the base wafer has to be exposed to vapor HF prior to bonding the cap wafer. Unfortunately, if the metal ring of the cap wafer is the proposed tin-copper, then the exposure to vapor HF is undesirable because this tin-copper is not a noble metal. If the metal ring of the cap wafer is the proposed the tin-nickel/gold, then the exposure to vapor HF would be more desirable because gold is a noble metal not affected by vapor HF exposure. Unfortunately, this proposed tin-nickel/gold metal ring implies that the tin-nickel metal under the gold bonding layer can form liquid nickel at a temperature of only 231° C., which is absolutely undesirable if the bonding is to be performed to the upper gold layer. The required precise indentation of the solder ring allowing the two substrates to be aligned, pressed together and heated to a “softening temperature” as to “stick” the two substrates together in the alignment and pre-bonding equipment, followed by the formal reflow of the solder ring in another batch reflow equipment makes the proposed process very complex, very costly to manufacture and of questionable reliability because the applied force is released before the actual reflow of the solder ring, thus allowing the various interfaces to be “de-stick” during manipulation and loading into the batch reflow oven.